LTC4263
8
4263fe
PIN FUNCTIONS
LED (Pin 1): Port State LED Drive. This pin is an open drain
output that pulls down when the port is powered. Under port
fault conditions, the LED will ash in patterns to indicate
the nature of the port fault. See the Applications Informa-
tion section for a description of these patterns. When the
LTC4263 is operated from a single 48V supply, this pin is
pulsed low with a 6% duty cycle during the periods when
the LED should be on. This allows use of a simple inductor,
diode, and resistor circuit to avoid excess heating due to
the large voltage drop from V
DD48
. See the Applications
Information section for details on this circuit.
LEGACY (Pin 2): Legacy Detect. This pin controls whether
legacy detect is enabled. If held at V
DD5
, legacy detect is
enabled and testing for a large capacitor is performed to
detect the presence of a legacy PD on the port. See the
Applications Information section for descriptions of legacy
PDs that can be detected. If held at V
SS
, only IEEE 802.3af
compliant PDs are detected. If left oating, the LTC4263
enters force-power-on mode and any PD that generates
between 1V and 10V when biased with 270糀 of detection
current will be powered as a legacy device. This mode is
useful if the system uses a differential detection scheme
to detect legacy devices. Warning: Legacy modes are not
IEEE 802.3af compliant.
MIDSPAN (Pin 3): Midspan Enable. If this pin is connected
to V
DD5
, Midspan backoff is enabled and a 3.2 second
delay occurs after every failed detect cycle unless the
result is open circuit. If held at V
SS
, no delay occurs after
failed detect cycles.
PWRMGT (Pin 4): Power Management. The LTC4263
sources current at the PWRMGT pin proportional to the
class of the PD that it is powering. The voltage of this pin
is checked before powering the port. The port will not
turn on if this pin is more than 1V above V
SS
. Connect the
PWRMGT pins of multiple LTC4263s together with a resistor
and capacitor to V
SS
to implement power management. If
power management is not used, tie this pin to V
SS
.
V
SS
(Pins 5, 6): Negative 48V Supply. Pins 5 and 6 should
be tied together on the PCB.
OSC (Pin 7) Oscillator for AC Disconnect. If AC discon-
nect is used, connect a 0.1糉 X7R capacitor from OSC to
V
SS
. Tie OSC to V
SS
to disable AC disconnect and enable
DC disconnect.
ACOUT (Pin 8): AC Disconnect Sense. Senses the port
to determine whether a PD is still connected when in AC
disconnect mode. If port capacitance drops below about
0.15糉 for longer than T
MPDO
the port is turned off. If
AC disconnect is used, connect this pin to the port with
a series combination of a 1k resistor and a 0.47糉 100V
X7R capacitor. See the Applications Information section
for more information.
OUT (Pins 9, 10): Port Output. If DC disconnect is used,
these pins are connected to the port. If AC disconnect
is used, these pins are connected to the port through a
parallel combination of a 1A diode and a 500k resistor.
Pins 9 and 10 should be tied together on the PCB. See the
Applications Information section for more information.
V
DD48
(Pin 11): 48V Return. Must be bypassed with a
0.1糉 capacitor to V
SS
.
SD (Pin 12): Shutdown. If held low, the LTC4263 is pre-
vented from performing detection or powering the port.
Pulling SD low will turn off the port if it is powered. When
released, a 4-second delay will occur before detection is
attempted.
ENFCLS (Pin 13): Enforce Class Current Limits. If held
at V
DD5
, the LTC4263 will reduce the I
CUT
threshold for
class 1 or class 2 PDs. If ENFCLS is held at V
SS
, I
CUT
remains at 375mA (typ) for all classes.
V
DD5
(Pin 14): Logic Power Supply. Apply 5V referenced
to V
SS
, if such a supply is available, or place a 0.1糉
bypass capacitor to V
SS
to enable the internal regulator.
When the internal regulator is used, this pin should only
be connected to the bypass capacitor and to any logic pins
of the LTC4263 that are being held at V
DD5
.
Exposed Pad (Pin 15, DE Package Only): V
SS
. Must be
connected to V
SS
on the PCB. The Exposed Pad acts as a
heatsink for the internal MOSFET.
(DFN/SO)
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